Speakers

Matt is a Research Fellow at Microchip and has 30 years of large-scale data center and networks experience. Matt has led many global standards groups related to data centers, the Internet and Telecommunications. Abstract: AI infrastructure is entering a pivotal architectural shift. As hyperscale, on-prem, and edge AI deployments push beyond the limits of conventional copper interconnects and fixed network assumptions, system designers now face multiple viable paths for building next-generation GPU fabrics. PCIe Gen 6, ESUN, copper transport, and optics are reshaping the design space for both scale-up and scale-out AI architectures. This session explores how platform architects may evaluate emerging fabric options across the dimensions that matter most: latency, power, reach, bandwidth density, scalability, cost, and deployment complexity. By connecting ongoing OCP work in high-speed switch fabrics, transport technologies, and reference architectures, this session will provide a practical framework for evaluating next-generation AI fabric choices. Attendees will leave with a clearer understanding of where copper, PCIe, Ethernet, CPO, and DWDM fit in future hyperscale, on-prem, and edge AI infrastructure—and how to select the right architecture for each deployment scenario.